The present invention relates generally to application specific integrated circuits (ASICs), and more particularly, to an embedded memory access method and system for application specific integrated circuits (ASICs).
In the past, memories were typically found only in discrete packages (e.g., a discrete DRAM). The discrete DRAM provides data, control and address ports for use by another integrated circuit (IC) to access the DRAM. In recent years with the proliferation of application specific integrated circuits (ASIC), there has been much interest in integrating the DRAM with the ASIC (referred to as an embedded DRAM architecture) into the same package in order to improve DRAM access rates. An embedded DRAM architecture provides faster access rates since package delays and board delays are no longer encountered.
FIG. 1 illustrates a system 1 that has functional blocks (e.g., block0 and block1) that require access to a discrete DRAM 6. The system 1 employs a prior art DRAM controller 7 for providing read and write access to the discrete DRAM 6. It is noted that a chip boundary 5 separates the discrete DRAM 6 and the controller 7. The DRAM controller 7 includes an arbiter 9 for receiving requests from the functional blocks and selectively granting access to the DRAM 6 to one of the functional blocks. A data and control steering unit 8 is provided for receiving sets of data, control and address signals from each of the functional blocks and a select signal from the arbiter 9. Based on these inputs, the data and control steering unit 8 generates or provides one of the sets of signals to the discrete DRAM 6. In this manner, the data and control steering unit 8 provides access to the discrete DRAM 6 to one of the functional blocks at any one time.
Unfortunately, this current architecture limits the width of the data bus accessing the discrete DRAM. Typically, the data bus to the discrete DRAM is 4 to 16 bits. In this example, the bus width is 8 bits. As can be appreciated, regardless of the width of the internal data bus, the DRAM bus causes a constriction of the bandwidth of the data flow.
In other words, there is a mismatch in the width of the data bus external to the ASIC and the width of the data bus internal to the ASIC. This mismatch causes the system to perform at a sub-optimal level from a bandwidth viewpoint.
In this situation, the DRAM controller typically receives a larger data word and employs multiple DRAM accesses to perform an operation. The DRAM controller requires some sort of data buffer to store the data while making the multiple accesses.
In the situation where an embedded DRAM that has a wide data bus is integrated with the ASIC, the DRAM controller is required to buffer internal data to be written to the DRAM since the internal data bus width is less than the DRAM data bus. Similarly, data read from the DRAM needs to be buffered and partitioned into smaller units and then provided to the functional blocks in the ASIC.
One approach is to re-design the internal ASIC data path in order to take advantage of the wide data bus. However, this approach would not only involve substantial cost and design effort, but also would limit the use of such an ASIC for embedded memory applications (i.e., a dedicated use for embedded memories). As can be appreciated, it would be desirable for there to be a mechanism that can take advantage of the wide data bus offered by an embedded DRAM architecture, and yet be flexible enough to support discrete DRAM applications.
Based on the foregoing, there remains a need for a memory access method and system for embedded memories that overcomes the disadvantages set forth previously.
According to one embodiment of the present invention, an application specific integrated circuit (ASIC) architecture for memory access is provided. A first functional block provides a first address, a first column address strobe signal, and a first read/write signal associated with a first memory access. A second functional block provides a second address, a second column address strobe signal, and a second read/write signal associated with a second memory access.
The ASIC architecture includes an embedded memory interface that is coupled to the first functional block and the second functional block. The embedded memory interface provides the first functional block and the second functional block access to an embedded memory either at the same time (referred to herein as concurrent access or simultaneous access) or at different times (referred to herein as consecutive or non-concurrent access). When predetermined conditions are met, the embedded memory interface provides the first functional block and the second functional block concurrent access to the embedded memory. When the predetermined conditions are not met, the embedded memory interface provides consecutive access to the embedded memory.
In one embodiment, the ASIC architecture also includes a discrete memory interface that is coupled to the first functional block and the second functional block. The discrete memory interface provides the first functional block and the second functional block access to a discrete memory at different times (also referred to herein as consecutive access or non-concurrent access). Preferably, the discrete memory interface and embedded memory interface are both specified by a register transfer language. During synthesis, either the discrete memory interface or the embedded memory interface is synthesized depending on whether the application has a discrete memory or an embedded memory.